MT6166 RF Design Notice for MT6572

▪ MT6166 RF QVL Plan

▪ MT6166 VS MT6168 & MT6167

▪ MT6166 function block

▪ MT6166 reference circuit (TDD & Common part)

▪ Connections between MT6166 and MT6572(BB)/MT6323 (PMIC)

▪ MT6166/MT6572/MT6323 RF layout guide (TDD & Common part)

▪ RF Driver Modification (2G/TDD)

▪ MT6166 reference circuit (FDD part)

▪ MT6166/MT6572/MT6323 RF layout guide (FDD part)

▪ RF Driver Modification (FDD)

▪ TD & WCMDA co-PCB

▪ Wireless de-sense design guide

MT6166 Function Block

MT6166 Transceiver RF Overview

全多模射频解决方案(gge/wcdma/tdscdma)通过3 gpp第8版

– SAW-less Quad-band support in GGE mode (GSM850/900/1800/1900)

– 3G-FDD bands support: Band 1,2,5,8.

– 3G-TDSCDMA bands support: Band 34,39,40

26MHz内部DCXO或外部VCTCXO操作(带有集成AFC DAC)

– Three low noise additional Clock Drivers for clocking connectivity / peripheral IC’s

– Ultra Low power 32KHz mode

支持关键的RX和TX规范的RF校准功能(Image rejection, LO feedthrough, DC offset)

MT6166 Reference Circuit

http://bbs.16rd.com/thread-15810-1-1.html

RF Design Note – MT6166 Pin assignment

RF Design Note – MT6166 Ball Map

--2G LB LNA input 為LB_RXP and LB_RXN, 2G HB and TD B34/B39 LNA input為HB_RXP and HB_RXN

Reference Circuit Schematic: MT6166 & 週邊元件 power

Bypass Cap should be put close to MT6166.

VRF18-1( 4 pins in MT6166) cap loading: 470nF X4 

VTCXO28-1 (2 pins in MT6166; 1 pin in BB DAC) cap loading: 470nFX 2 (MT6166)+ 100nF (BB) 

VIO18 (1 pins in MT6166 ; many pins in BB & others ) cap loading: 1uF

Note: Only design value--finalized Cap value will be updated later

Reference Circuit Schematic: MT6166 Power

下表包括MT 6166中每个功率引脚的近似最大RF电流消耗。需要小心每个电源销的旁路帽放置/值和布局跟踪宽度！

请注意，VXODIG是一个电源引脚，而不是数字控制引脚！(与VIO 18或VTCXO 28-1共用旁路盖)

XMODE，CLK_SEL，ENBB，32K_en是数字控制引脚

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